Same repairs.
New domains.

Digital chip designs · Amaranth HDL → Verilog

9 bugs in 8 designs.

A counter, Gray-code converters, an 8-bit ALU, a FIFO, a UART transmitter, a PWM generator, a debouncer and a CRC-8 unit, written in Amaranth HDL and checked cycle by cycle by 26 simulation testbenches.

Same 9/9, at 58% fewer tokens.

/* Generated by Amaranth Yosys 0.50 (PyPI ver 0.50.0.0.post129, git sha1 b5170e139) */

(* top =  1  *)
(* generator = "Amaranth" *)
module pwm(clk, rst, out, duty);
  reg \$auto$verilog_backend.cc:2355:dump_module$1  = 0;
  wire \$1 ;
  wire [3:0] \$2 ;
  reg [2:0] \$3 ;
  input clk;
  wire clk;
  input [3:0] duty;
  wire [3:0] duty;
  output out;
  wire out;
  reg [2:0] phase = 3'h0;
  input rst;
  wire rst;
  assign \$1  = phase == 3'h7;
  assign \$2  = phase + 1'h1;
  assign out = phase < duty;
  always @(posedge clk)
    phase <= \$3 ;
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$1 ) begin end
    (* full_case = 32'd1 *)
    if (\$1 ) begin
      \$3  = 3'h0;
    end else begin
      \$3  = \$2 [2:0];
    end
    if (rst) begin
      \$3  = 3'h0;
    end
  end
endmodule

The planted bugs

Circuit schematics · netlists checked by circuit simulation

8 bugs in 7 circuits.

A netlist is the text form of a schematic, the file KiCad exports and SPICE simulates. A small simulator (Modified Nodal Analysis, checked against hand calculations) tests each circuit against its spec.

Same 8/8, at 64% fewer tokens.

* Voltage divider: 5 V supply down to a 3.3 V logic reference
V1 in 0 DC 5
R1 in out 10k
R2 out 0 20k

The planted bugs

A larger schematic · one netlist, shared power rails

A sensor circuit, brought up in simulation.

USB 5 V in, an LM317-style regulator set to 3.3 V, an NTC temperature sensor with an op-amp buffer and a 1 kHz anti-aliasing filter into the microcontroller's ADC, a reset circuit, power and status LEDs, and I²C pull-ups. 11 bring-up checks, the ones an engineer runs on a new board: is the rail 3.3 V, are the LEDs safe, does the sensor read right, is anything over the MCU's 3.6 V limit.

Open the circuit explorer: the circuit illustrated, every bug, the agent's steps →

The circuit: board.cir, checked by test_board.py. Schematic level only: no PCB layout.

6, 7 → 8, 8 of 8 solved.

Where the gap comes from: the original worker refused BD01 (both runs) and BD02 (one run) in a single turn, replying that a sensor-board report is "a hardware issue, not a bug in the Python library", without running a check. Both workers get the same prompt. The repaired worker's learned workflow starts by running the tests, so it engaged and fixed all 8.

The planted bring-up bugs

Security · every fix checked by an exploit

8 vulnerabilities, closed or not.

A small notes service with eight vulnerability classes (SQL injection, path traversal, unpickling client data, broken access control, stored XSS, predictable reset tokens, open redirect, double-extension uploads). A fix counts only if the exploit fails and the feature still works; the fix audit flags any patch that touches the tests.

Same 8/8, at 60% fewer tokens.

def test_exploit_sql_injection_returns_nothing():
    conn = connect(USERS)
    assert find_user(conn, "x' OR '1'='1") == []
    assert find_user(conn, "x' UNION SELECT name, role FROM users --") == []

The planted vulnerabilities

What this shows, and what it doesn't

The gain is efficiency.

Both workers fix every chip-design and schematic bug, so these sets show no gain in what gets solved. What carried over is how: the self-repaired worker reads less, edits precisely and stops when the tests pass, so it needs far fewer turns and tokens. Two runs per worker; the sets are small; everything is simulated, not built on a physical board.